1. Field of the Invention
This invention relates to a data processing device and more particularly to a data processing device for processing a data sequence obtained by sampling an information signal.
2. Description of the Prior Art
A data sequence consisting of data arranged in the direction of time, is obtained when an information signal, such as an audio or video signal, is sampled. Such a data sequence is generally transmitted in serial order. However, incorrect data sometimes arise among the data obtained via a transmission system. In that event, there have been employed methods, called interpolation methods, in which the incorrect data are replaced with presumed data, called interpolation data, which are obtained from correct data before and/or after the incorrect data.
For example, known interpolation methods for replacing incorrect data arising within a data sequence obtained by sampling an audio signal, include a pre-holding method in which a data immediately before an incorrect rate data, is used as it is for interpolation; an average value interpolation method, in which a data obtained by averaging data immediately before and after an incorrect rate data, is used for interpolation; and a tertiary interploation method in which a data obtained from at least four data near an incorrect rate data is used for interpolation.
The accuracy or proximity of the interpolation data to a proper data is the lowest in accordance with the pre-holding method, better in the average value interpolation method and best in the tertiary interpolation method. However, the scale of hardware required increases with the accuracy attainable. These methods are thus employed according to the kind of the information signal to be processed and to the scale allowable for the equipment to be used.
FIG. 1 of the accompanying drawings schematically shows an arrangement of a typical conventional data processing device which uses the average value interpolation method in replacing incorrect data. Referring to FIG. 1, each of latching circuits 2 and 4 is arranged to delay a data supplied thereto by one sampling period. An average value computing circuit 6 is arranged to produce, through computation, a data of an average value obtained from a data supplied to the latching circuit 2 and a data produced from the latching circuit 4. A data selector 8 is arranged to select either the data produced from the latching circuit 2 or the data produced from the average value computing circuit 6. An input terminal 10 is arranged to receive timing clock pulses. Another input terminal 12 is arranged to receive a known error detection signal which indicates an incorrect or a correct data. Another latching circuit 14 is arranged to delay, by one sampling period, the error detection signal. As is well known, the error detection signal is obtained by checking a parity word or CRCC. For example, in the case that the data supplied to the latching circuit 2 is incorrect, an input "1" is supplied to the terminal 12 and, if the data is correct, an input "0" is supplied to the terminal 12. The data selector 8 produces the output data of the average value computing circuit 6 when the output of the latching circuit 14 is at "1" and produces the output data of the latching circuit 2 when the output of the latching circuit 14 is at "0".
If the data produced from the latching circuit 2 is correct, the output of the latching circuit 14 is at "0" and the data selector 8 selects the output data of the latching circuit 2 as it is. In the event that the data produced from the latching circuit 2 is incorrect, the output of the latching circuit 14 becomes "1". Then, the output data of the average value computing circuit 6 is selected by the data selector 8. Since the output data of the average value computing circuit 6 is a data of the average value of data immediately before and immediately after the output data of the latching circuit 2, the data processing device thus performs average value interpolation.
The above-stated average value computing circuit 6 consists of, for example, a full adder and a 1/2 multiplier operating by one bit shift. In this instance, if the least significant bit of the data supplied to the 1/2 multiplier is "1", the data produced from the average value computing circuit 6 is inevitably obtained by rounding off the result of computation. This will be further described below:
Assuming that each data consists of four bits, a data A which is immediately before an incorrect data B is 1101 (2) and a data C which is immediately after the incorrect data B is 1101 (2), in computing (A+C)/2 by the above-stated method, A+C becomes 10110 (2). With the value down shifted by one bit, it becomes 11011 (2). According to the decimal system, it becomes (13+9)/2=11. Therefore, a proper average value of the data can be obtained in this instance. In another instance, however, if the data A is 1101 (2) and that data C is 1000 (2), for example, 10101 (2) is obtained by computing A+C and then 1010 (2) is obtained as the average value data. Then, in the decimal system, this is expressed as (13+8)/2=10, which is not a proper average value as the fractional portion of the result of computation is lost. Accordingly, in the event of many incorrect data, the average value interpolating data processing device inevitably shifts a proper information signal downward before it is produced.
In other conventional data processing devices which are arranged differently from the above-stated one, the values of the interpolating data are also either rounded up or rounded off when they are computed. Therefore, their outputs have been also shifted from a proper information signal. Besides, in cases where positive and negative portions of a signal are produced at about the same rate with reference to a zero level, like in the case of an analog audio signal, this shift results in an undesirable DC component.
Further, it is impossible to determine whether a proper information signal is larger or smaller than an average value data. Therefore, the down shifted or rounded off output data might increase an error from an original analog signal. This also has sometimes resulted in an unnatural high frequency component. The conventional arrangement to round up the fraction instead of rounding it off also has presented these problems.